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Computer Architecture II

Module code: CSU34021 · Semester: Semester 1

Questions by Year​

0 of 6 done · tick papers and add notes as you go

Papers open on tcd.ie (sign in to TCD first).

Topics

  • IA32 and x64 assembly: registers, stack, calling conventions LO1
  • RISC vs CISC; the RISC-1 architecture LO1–2
  • Pipelining, hazards and instruction-level performance LO2
  • Virtual memory, page tables, TLBs and MMUs LO3
  • Caches: associativity, locality, profiling LO4–5
  • Performance tools: perf, valgrind LO5
  • Multicore, NUMA, coherence (MESI) and memory consistency LO6–7
Learning outcomes (exam covers LO1–7)
  1. Write and reason about assembly programs
  2. Describe the instruction pipeline and its hazards
  3. Explain virtual memory, address translation and MMUs
  4. Analyse cache organisation and locality
  5. Profile code with performance tools
  6. Understand multicore architecture and performance
  7. Evaluate cache coherence and synchronisation

Summarised from the module descriptor, checked November 2026.