VLSI Design

Module code: EEP55C32 · Semester: Semester 2

Resources

• Module descriptor (TCD)

Questions by Year

0 of 1 done · tick papers and add notes as you go

• 2025/26

Papers open on tcd.ie (sign in to TCD first).

Topics

• ASIC design flow from HDL to GDSII LO1
• Logic synthesis and optimisation for area, speed and power LO2
• Floorplanning and placement LO1–2
• Timing and power analysis LO3
• Verification and test LO3

Learning outcomes (exam covers LO1, LO3–4)

1. Know open-source and industrial design flows from RTL to GDSII
2. Use design tools confidently and understand area, performance and power optimisation
3. Understand timing, performance, power, verification and test issues
4. Be ready to work as a junior VLSI engineer with EDA tools

Summarised from the module descriptor, checked November 2026.