Integrated Systems Design

Module code: EE5M01 · Semester: Semester 1

Resources

• Module descriptor (TCD)

Questions by Year

0 of 5 done · tick papers and add notes as you go

• 2025/26
• 2024/25: Paper 1 · Paper 1
• 2022/23
• 2018/19

Papers open on tcd.ie (sign in to TCD first).

Topics

• Finite state machines with datapath LO2
• Verilog HDL LO1–2
• Automated testbenches and golden vectors LO3
• Finite precision and bit-width in fixed-point designs LO4–5
• Moving MATLAB DSP designs onto an FPGA LO1, LO7
• FPGA memory LO6
• Hardware-software interface, accelerators and high-level synthesis LO7

Learning outcomes

1. Build and verify a synchronous DSP system in Verilog
2. Build and test complex FSMs in Verilog
3. Automate pass/fail testbenches
4. Analyse finite precision effects in digital filters
5. Make fixed-point design decisions under constraints
6. Analyse memory needs for FPGA designs
7. Target sequential designs to FPGA hardware

Summarised from the module descriptor, checked November 2026.