Digital Systems Design

Module code: EEU33C07 · Semester: Semester 2

Resources

• Module descriptor (TCD)

Questions by Year

0 of 12 done · tick papers and add notes as you go

• 2025/26
• 2024/25
• 2022/23
• 2021/22
• 2020/21
• 2019/20
• 2018/19
• 2017/18 (old code EE3C07)
• 2016/17 (old code EE3C07)
• 2014/15 (old code EE3C07)
• 2013/14 (old code EE3C07)
• 2012/13 (old code EE3C07)

Papers open on tcd.ie (sign in to TCD first).

Topics

• Combinational and sequential logic LO1
• Finite state machines LO2
• Digital design flows and trade-offs LO3
• FPGA architecture and resources LO7
• Verilog HDL LO4, LO8
• Testbenches and test plans LO5–6
• Computer arithmetic (revision from first year) LO1

Learning outcomes (exam covers LO1–8)

1. Tell combinational and sequential circuits apart
2. Design state machines to control complex systems
3. Understand digital design flows and their trade-offs
4. Write synthesisable Verilog
5. Write Verilog testbenches
6. Write test cases and test plans
7. Target a Verilog design to an FPGA
8. Analyse and debug Verilog modules

Summarised from the module descriptor, checked November 2026.